1. Field of the Invention
The present invention relates to semiconductor flash memory, and more particularly to programming multiple level cell (MLC) flash memory, including NAND and NOR type arrays.
2. Description of the Related Art
Flash memory is widely used in today""s electronic products especially for portable applications as a result of its non-volatility and in system re-programmability. The basic structure of a flash memory cell contains a control gate, a drain diffusion region and a source diffusion region on the substrate to form a transistor with a floating gate under the control gate to be the electron storage device. The channel region lies under the floating gate with a tunnel oxide layer between the channel and floating gate that is the insulation layer. The energy barrier of the tunnel oxide can be overcome by applying a sufficiently high electric field across the tunnel oxide. This allows electrons to pass through the tunnel oxide, which is used to change the number of electrons stored in the floating gate. The number of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. The Vt of a cell is used to represent the stored data of the cell.
To change the Vt of a cell to a higher or lower value, the number of the electrons stored in the floating gate is increased or decreased by applying proper voltages to the control gate, the drain and source regions, and the channel region to cause electrons to move between one or more of these nodes and through the tunnel oxide layer to the floating gate. When the electrons are moved between the channel region and the floating gate, it is referred to as a channel operation. When the electrons are moved between the drain or source region and the floating gate, it is referred as an edge operation since it takes place on the overlap region between the edge of the floating gate and the drain or source region.
When changing the Vt of a flash memory cell, two operations are required. The first operation, called an erase operation, is applied to a large number of cells called a block. The second operation, called a program operation, is applied to a smaller number of cells called a page. The erase operation will change the Vt of all the cells in a selected block to a high Vt or a low Vt, depending on the design consideration. The program operation will change the Vt of selected cells to a value opposite that of the erase operation. While the erase operation is performed on a collective basis, the program operation must be bit selectable in order to change the Vt of a individual cell according to the desired data. There are various mechanisms and technologies suitable for erasing and programming different types of flash memories including the Fowler-Nordheim (F-N) tunneling mechanism, which is chosen because of its extremely low power consumption.
In U.S. Pat. No. 5,748,538 (Lee et al.) a flash memory cell array is directed to the use of Fowler-Nordheim tunneling for programming the cells. The memory cell stores two levels of threshold voltage (Vt). Both over erase and over programming repair capability is discussed. U.S. Pat. No. 5,768,188 (Park et al.) is directed to a multi-level flash memory cell (MLC) array using a conventional MLC programming scheme that uses a serial stepwise word line voltage to control the programming time as well as the Vt distribution of MLC.
A flash memory, which stores two levels of Vt in a cell, is called a single bit cell. For example, assume the low Vt level of a cell is below +2V and the high Vt level is above +4V. During a read operation, a voltage between the two Vt levels, e.g. +3V, is applied to the selected word line and in turn to the control gate of the selected cell to check the Vt of the cell. If the cell is in a low Vt state, the voltage applied to the control gate will turn on the channel of the selected cell and allow current to flow through the channel from the drain to the source. If the cell is in a high Vt state, the voltage applied to the control gate will not be able to turn on the channel of the cell, thus preventing current flowing from drain to source. With the source region grounded, the selected bit line and the drain region of the selected cell is biased at around +1V. A sense amplifier is used to detect the current flowing on the bit line and converts the amount of current flow into logical xe2x80x9c0xe2x80x9d or logical xe2x80x9c1xe2x80x9d data.
A Multiple Level Cell (MLC) technology has attracted a lot of attention due to its cost efficiency. By storing 2N discrete levels of Vt, the MLC can store N bits of data per cell, thus reducing the equivalent cell size to 1/N. Because of the multiple bits of data per cell, the MLC has become one of the best candidates in mass storage applications that typically require high density such as 512 Mb and beyond. FIG. 1 shows an example of typical Vt distribution of 4-level MLC. The Vt of the cell is divided into four levels to represent data (00), (01), (10) and (11). When read, three reference voltages Vref1, Vref2 and Vref3 are applied to check the Vt level.
The implementation of MLC requires a key design technique, which is how to accurately control the Vt distribution of the programmed cell. Because the Vt distribution for each level and the margin between the levels is much smaller than that of the single bit cell, a highly accurate programming scheme is needed to achieve the tight Vt control. The conventional programming scheme used for single bit cell is not suitable for this purpose. When programming a single bit cell, typically the word line and bit line are coupled to fixed voltages. For example, the word line is coupled to +17V and the bit line is coupled to +0V. This voltage condition will cause the Vt of the programmed cell to increase. The final programmed Vt is controlled by the programming time. However, it is very difficult to achieve the tight Vt distribution requirement of MLC by using this approach.
FIG. 2 shows a typical curve of programmed Vt vs programming time. As the figure shows, the relationship between the programmed Vt and programming time is approximately an exponential curve; a higher Vt requires several orders longer time to program than the lower Vt. For example, programming Vt to +3.5V takes 200 us, the same program condition to program the Vt to +0.5V will take about only {fraction (1/1000)} of the time, or 200 ns. The extremely short programming time is very difficult to control and can easily end up being over programming. On the other hand, if the word line voltage is reduced to +11V to slow down the programming time for Vt so that +0.5V takes 200 us, the programming time for +3.5V will become as long as 200 ms.
FIG. 3A shows a stepwise word line voltage to control the programming time and Vt distribution of an MLC. FIG. 3B shows the voltage setup for the word line and bit lines. Assuming four cells, M1, M2, M3 and M4 are selectively programmed to a Vt of +0.5V, +1.5V, +2.5V and +3.5V, respectively. The program operation is divided into four sequential steps. In the first step, the word line voltage is coupled to a voltage of +11V, and the bit lines of all the four cells, VBL00, VBL01, VBL10 and VBL11, are coupled to 0V. The voltages of the source lines VSL00, VSL01, VSL10 and VSL11 can be either coupled to the same voltage as the corresponding bit lines or remain floating. Because the word line is coupled with a high voltage during the program operation, the channels of the selected cells will be turned on and pass the bit line voltages to the source lines. The source lines must be coupled to the same voltages as the bit line, or remained floating to prevent current leakage. The bias condition will program the Vt of all the four cells to +0.5V in approximately 200 us.
Continuing to refer to FIGS. 3A and 3B, in the second step, the word line voltage is increased to about +13V to program the Vt of the cells to +1.5V. Since the cell M1 has reached its target Vt=+0.5V, its bit line voltage, VBL00, will be coupled to a positive voltage such as +6V to reduce the voltage difference between its word line and bit line to inhibit the cell from being further programmed. For cells M2, M3 and M4, bit lines connected to these cells are coupled to 0V to program the Vt to +1.5V. According to the curve of the programming time vs. Vt shown in FIG. 2, if a fixed word line voltage is applied, it would take about one order of magnitude longer time to program the Vt of the cells to +1.5V than +0.5V. However, because a higher word line voltage is applied, the programming time of this step will be shortened by about one order of magnitude.
Consequently, it will take about the same programming time as the first step, approximately 200 us, to program the Vt of the cells +1.5V. Similarly, the word line voltage is ramped up from +11V, +13V, +15V and +17V in the four steps, to program Vt of the cells to +0.5V, +1.5V, +2.5V and +3.5V, respectively. The bit line voltage for the cell selected to be programmed is coupled to +0V, and the cells not selected to be programmed are coupled with an inhibit bit line voltage of +6V.
FIG. 4 shows the curve of programmed Vt vs. programming time according to the stepwise word line voltage programming scheme of shown in FIGS. 3A and 3B. The proper stepwise word line voltage is selected so that the programming time for each Vt step is similar to that of programming the single bit cell. The curve shows that stepwise word line voltage successfully controls the programming time for each Vt step at approximately 200 us. The overall programming time for the highest Vt level, +3.5V, is about 4 times of that for the lowest Vt level +0.5V. Comparing the stepwise approach with the single bit cell programming as shown in FIG. 2, the programming time for the Vt level +3.5V is about 1000 times longer than that for the Vt level +0.5V. Since the stepwise approach programs the different Vt levels of cells with different word line voltages step by step. This approach is called a xe2x80x9cserial programming schemexe2x80x9d.
The serial programming scheme has the two significant drawbacks. First, the programming time has to be increased 2N times compared with the single bit cell. Since the programming is performed step by step for each Vt level. For a MLC having 2N Vt levels, it will take 2N times longer than the single bit cell to program, and because programming is typically critical for most of the applications, the longer programming time has become a serious problem for MLC applications. Second, the program disturb time is increased 2N times as compared with the single bit cell. This is because when a Vt level is programmed, all the bit lines of deselected cells have to be coupled with an inhibit voltage, e.g. +6V, to reduce the gate to drain voltage to prevent the cells being programmed. However, this inhibit bit line voltage will be shared by all the cells on a bit line. For the other cells on deselected word lines, the word line voltage is coupled with +0V, thus the bit line voltage will cause the Vt of these cells to decrease over time. This phenomenon is called xe2x80x98bit linexe2x80x99 disturb. This disturb problem becomes extremely important and severe for MLC since the Vt margin between each level is small, e.g. 0.6V, compared with that of a single bit cell, e.g. 3V. Since the programming time is increased by 2N orders of magnitude, the disturb time is also increased by 2N orders of magnitude.
A technical paper xe2x80x9cA 98 mm2 3.3V 64 MB Flash Memory with FN-NOR Type 4-level Cellxe2x80x9d, Ohkawa et al., ISSCC, 1996,Session 2, TP 2.3, pp 36-37 is directed to parallel programming of MLC flash memory cells. During programming a negative high voltage, e.g. xe2x88x929V, is coupled to a word line and different positive high voltages, e.g. +6V, +5V, +4V and +0V, are coupled to the bit lines to decrease the Vt of the selected cells. Since the voltage of the word line is a high negative value, it will turn off the channel of the cell, and the channel region then will remain at the same voltage as the substrate, typically 0V. The selected bit line is coupled to a positive high voltage, and electrons will be injected from the floating gate to the bit line junction through the edge of the tunnel oxide layer overlapped with the bit line junction. This condition is known as xe2x80x98edge programmingxe2x80x99, and it has the following drawbacks. 1) The programmed cell is under a severe breakdown condition. Since the word line is coupled to a high negative voltage, the channel of the selected cell is turned off, which can cause the high positive voltage applied to the bit line junction to breakdown. 2) As a result of the breakdown condition, the bit line diffusion of the memory cell requires a lightly doped deep junction to sustain the higher breakdown voltage, causing the size of the cells to be increased. 3) The programming bias condition causes a band-to-band tunneling (BTBT) current to occur in the drain junction. The tunneling current is several times the programming current, and will leak from the drain junction to the substrate. This will require an increase of the on chip pump supply current. If the pump cannot sustain the BTBT current, the bit line voltage will drop and cause programming failure. 4) The programming bias condition can also produce a punch through condition. The high positive voltage applied to the bit line junction may punch though the channel voltage of the cell gated by the negative word line bias and touch the source junction. To prevent this from happening, the channel length of the cell must be increased, which limits the cell""s scalability. 5) The programming bias condition can cause impact ionization to occur in the channel edge near the drain junction. This will generate electron hole pairs, and due to the negative biased gate voltage. The holes will be accelerated and injected into the floating gate. From experimental observation, it has been shown that part of the injected holes can be trapped inside the tunnel oxide and cause an oxide rupture. This phenomenon is known to be the major cause of the degradation of flash memory cell erase and program cycle degradation.
An objective of the present invention is to parallel program a flash memory using multiple level cells (MLC), where a plurality of cells is programmed at the same time.
Another objective of the present invention is to parallel program a flash memory using MLC, where a plurality of cells of a NOR type or a NAND type cell array are programmed at the same time.
A yet another objective of the present invention is to eliminate the aforementioned problems associated with programming MLC flash memory cells.
Still another objective of the present invention is to parallel program an MLC flash memory using a channel tunneling operation.
Still yet another objective of the present invention is to parallel program an MLC using a fixed high word line voltage and multiple bit line voltages.
A further objective of the present invention is to use a plurality of bit line voltages to program a plurality of Vt levels on a plurality of MLC flash memory cells.
Still a further objective of the present invention is to program all cells on a word line to a plurality of Vt voltages at one time.
Yet a further objective of the present invention is to apply a higher gate to channel voltage to cells requiring a higher Vt.
Yet another objective of the present invention is to select bit line voltages such that the programming speed for the different VT levels are similar.
Yet another objective of the present invention is to accurately control programming time and produce a tight Vt distribution.
Yet still another objective of the present invention is to reduce the overall programming time to xc2xdN compared to prior art, where N is the number Vt levels to be programmed.
Yet still another objective of the present invention is to reduce disturb time xc2xdN compared to prior art.
Yet still another objective of the present invention is to simplify design of the programming pulse and programming algorithm.
The present invention provides parallel programming of MLC flash memory cells, which are coupled to a common word line with a fixed high positive voltage and by coupling different voltage levels to the bit lines of the flash memory cells. The high word line voltage will turn on the channel of a cell, and the bit line voltage coupled to the drain of cells produces a channel voltage that varies from cell to cell depending upon the value of the bit line voltage. A cell requiring a higher Vt has a higher gate to channel voltage, which shortens the programming time for the higher Vt cell. A cell requiring a lower Vt has a lower gate to channel voltage, which slows the programming time for the low Vt cell. The bit line voltages are so chosen so that all programming time for the lowest Vt cell to the highest Vt cell is accomplished in approximately the same amount of time. This facilitates accurate programming and tight Vt distributions.